1. Field of the Invention
The present invention relates to a semiconductor memory read circuit for changing the word voltage of a multilevel storage semiconductor memory by stages such as from second stagexe2x86x92first stagexe2x86x92third stage or from fourth stagexe2x86x92second stagexe2x86x92sixth stagexe2x86x92first stagexe2x86x92third stagexe2x86x92fifth stagexe2x86x92seventh stage. Particularly, the present invention relates to a multilevel storage semiconductor memory read circuit capable of reducing power consumption by shortening sense amplifier operation time.
2. Description of the Related Art
A conventional read method in a multilevel memory is to actuate a sense amplifier for each of the word voltages at respective stages and to obtain ON/OFF outputs according to the threshold voltage VT of a multilevel cell. Then, the output results of the word voltages at the respective stages are latched by latch circuits, the respective latched outputs are logically operated by an encoder and data is transmitted to an output circuit
FIG. 1 is a circuit diagram showing one example of the conventional read circuit. FIG. 2 is a truth table of the circuit diagram. FIG. 3 is a timing chart showing circuit operation. The output of a cell 712 of a read circuit 740 is inputted into a sense amplifier 713 and inputted from the sense amplifier 713 into a latch circuit group 711. The latch circuit group 711 has latch circuits 742, 741 and 743 for first to third stages, respectively. The outputs L1 and L3 of the first-stage latch circuit 742 and the third-stage latch circuit 743, respectively, are inputted into an EOR logic gate 715 of an encoder circuit 717. The output of the EOR logic gate 715 and the output L2 of the second-stage latch circuit 741 are inputted, as superordinate data B1 and subordinate data B0, into an output circuit 718, respectively.
Next, the operation of the conventional read circuit will be described. First, at an interval T1, the level of a signal xc3x82 for setting a word voltage at the second stage is xe2x80x9cHxe2x80x9d and the sense amplifier 713, therefore, reads a cell when the word level is at the second stage. As shown in the truth table of FIG. 2, since a VT1 cell is turned on at the second-stage word level, a xe2x80x9cLxe2x80x9d data indicating that the read cell is turned xe2x80x9cONxe2x80x9d is outputted from the sense amplifier.
Next, when the interval moves from T1 to T2, the level of the signal xc3x82 inputted into the latch circuit 741 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d. Due to this, the output data of the sense amplifier 713 is latched by the second-stage latch circuit 741 and transmitted, through the encoder circuit 717, to the output circuit 718 as the subordinate data B0. Namely, at this point, the subordinate data B0 on the truth table shown in FIG. 2 is determined. Also, since the level of the latch signal xc3x82 is xe2x80x9cLxe2x80x9d during the intervals T2 and T3, the level of the latch data L2 remains xe2x80x9cLxe2x80x9d until an interval T4.
Further, at the interval T2, the level of a signal xc3x81 for setting a word voltage at the first-stage voltage is xe2x80x9cHxe2x80x9d and the sense amplifier 713, therefore, outputs data when the word level is at the first stage.
Next, when the interval moves from T2 to T3, the level of the signal xc3x81 inputted into the latch circuit 742 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d and the output data of the sense amplifier 713 is, therefore, latched by the first-stage latch circuit 742, As in the case of the above, since the level of the latch signal xc3x81 is xe2x80x9cLxe2x80x9d during the intervals T3 and T4, the latch data L1 is maintained until the next interval T5.
At the interval T3, the level of a signal xc3x83 for setting a word voltage at the third-stage voltage is xe2x80x9cHxe2x80x9d and the sense amplifier 713, therefore, outputs data when the word level is at the third stage.
Next, when the interval moves from T3 to T4, the level of the signal xc3x83 inputted into the latch circuit 743 changes from xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d. Due to this, the output data of the sense amplifier 713 is latched by the third-stage latch circuit 743. As in the case of the above, since the level of the latch signal xc3x83 is xe2x80x9cLxe2x80x9d during the intervals T4 and T5, the latch data L3 is maintained until the next interval T6. The latch data is then transmitted, through the third-stage latch circuit 743, to the encoder circuit 717, operated with the first-stage latch output L1 by the EOR logic gate 715 and the superordinate data B1 is thereby determined and transmitted to the output circuit 718. Namely, at this point, the superordinate data B1 on the truth table shown in FIG. 2 is determined. Through the above-stated circuit operation, the sense amplifier 713 in this example constantly operate with word voltages at the respective stages when reading one cell 712.
The conventional circuit, however, has the following disadvantages. It is obvious that a cell turned on as a result of reading the second-stage cell is also turned on at the third-stage word voltage. In addition, it is obvious that a cell turned off as a result of reading the second-stage cell is also turned off at the first-stage word voltage. However, since the sense amplifier constantly operates to latch sense amplifier outputs at the respective word voltages, excessive power is consumed.
The basic constitution of a multilevel storage semiconductor memory is described in Japanese Patent Application Laid-Open No. 1-196791. A multilevel memory capable of reducing the number of sense amplifiers to allow reducing chip area is described in Japanese Patent Application Laid-Open No. 7-37393. A multilevel memory intended to accelerate data reading speed is described in Japanese Patent Application Laid-Open No. 10-11982. A semiconductor memory capable of reading minute multilevel data is described in Japanese Patent Application Laid-Open No. 11-110974. None of these prior arts described in the publications are, however, intended to reduce power consumption based on sense amplifier operation.
It is an object of the present invention to provide a multilevel storage semiconductor memory capable of removing excessive sense amplifier operation and reducing sense amplifier power consumption by using sense amplifier operation stop circuit and latch input correction circuit.
A multilevel storage semiconductor memory read circuit according to the present invention is for applying a plurality of stages of word voltages to one cell and latching data according to respective word voltage levels, and comprises a sense amplifier reading the cell; a latch circuit group consisting of a plurality of latch circuits and latching the data according to the respective word voltage levels; an encoder circuit converting outputs of the latch circuits into binary data; a stop and correction circuit stopping a circuit operation of the sense amplifier when a different-stage latch circuit performs a read operation based on an output result of a specified-stage latch circuit, and applying a signal expected to be outputted from the sense amplifier, which is being stopped, as an input signal L0 of the latch circuit group.
In case of, for example, a four-level cell with three latch circuits of the first-stage latch circuit, the second-stage latch circuit and the third-stage latch circuit, the cell turned on as a result of reading the cell at the second stage has a lower cell threshold value than a second-stage word voltage and the cell is obviously turned on when read at a third-stage word voltage higher than the second-stage word voltage. The cell turned on as a result of reading the cell at the second stage has a higher cell threshold value than the second-stage word voltage and the cell is obviously turned off when read at the first-stage word voltage lower than the second-word voltage. According to the present invention, the operation of the sense amplifier is stopped only in such a case of reading the cell as to satisfy these two conditions. In addition, by supplying data expected to be outputted from the sense amplifier during a sense amplifier stop period from the latch input correction transistor, it is possible to reduce power consumption.
For example, if a read result of the cell at the second stage is xe2x80x9cOFFxe2x80x9d when a control signal xc3x81 for reading the cell at a first-stage word voltage becomes xe2x80x9cHxe2x80x9d, it is estimated that the cell threshold value is higher than the second-stage word voltage and that the result is xe2x80x9cOFFxe2x80x9d. Thus, the stop and correction circuit stops the operation of the sense amplifier and applies an xe2x80x9cHxe2x80x9d signal indicating xe2x80x9cOFFxe2x80x9d to a latch input signal line. In addition, if the read result of the cell at the second stage is xe2x80x9cONxe2x80x9d when a level of a control signal xc3x83 for reading the cell at the third-stage word voltage becomes xe2x80x9cHxe2x80x9d, it is estimated that the cell threshold value is lower than the second-stage word voltage and that the result is xe2x80x9cONxe2x80x9d. Thus, the stop and correction circuit stops the operation of the sense amplifier and applies an xe2x80x9cLxe2x80x9d signal indicating xe2x80x9cONxe2x80x9d to the latch input signal line.
To be specific, the multilevel storage semiconductor memory read circuit is constituted such that the latch circuit group has a first-stage latch circuit, a second-stage latch circuit and a third-stage latch circuit; the specified-stage latch circuit is the second-stage latch circuit; the stop and correction circuit comprises: a first NAND logic gate inputting an output L2 of the specified-stage latch circuit and inputting a first-stage word voltage control signal xc3x81; a second NAND logic gate inputting a specified-stage latch circuit output L2 at one of input terminals through a first inverter and inputting a third-stage word voltage control signal xc3x83 at the other input terminals; a first P-channel transistor having, as a drain, an input line L0 of the latch circuit group and a source set at a VCC level; a first N-channel transistor having, as a drain, the input line L0 of the latch circuit group and a source set at a GND level; a third NAND logic gate inputting an output of the first NAND logic gate and an output of the second NAND logic gate; a second P-channel transistor having, as a drain, a VCC-side power supply wiring VS supplying power to the sense amplifier, and a source set at the VCC level; and a second N-channel transistor having, as a drain, a GND-side power supply wiring GS of the sense amplifier and a source set at the GND level, and that an output of the third logic gate is connected to a gate of the second P-channel transistor, the output of the third logic gate is connected to a gate of the second N-channel transistor through a second inverter, the output of the first logic gate is connected to a gate of the first P-channel transistor, and the output of the third NAND logic gate is connected to a gate of the first N-channel transistor through a third inverter.
In this case, the encoder circuit can be constituted to have an EOR logic gate inputting an output of the first-stage latch circuit and an output of the third-stage latch circuit; to output an output of the EOR logic gate to the output circuit as superordinate data B1, and to output an output of the second-stage latch circuit to the output circuit as subordinate data B0.
Further, the multilevel storage semiconductor memory read circuit can be constituted such that the latch circuit group has the first-stage latch circuit to an (nxe2x88x921)th-stage latch circuit; the specified-stage latch circuit is an (n/2)th-stage latch circuit; and the stop and correction circuit comprises: a first OR logic gate inputting a first-stage word voltage control signal xc3x81 to an (n/2xe2x88x921)th-stage word voltage control signal xc3x8(n/2xe2x88x921); a second OR logic gate inputting an (n/2+1)th-stage word control signal xc3x8(n/2+1) to an (nxe2x88x921)th-stage word voltage control signal xc3x8(nxe2x88x921); a first NAND logic gate inputting an output L(n/2) of the (n/2)th-stage latch circuit and an output of the first OR logic gate; a second NAND logic gate inputting, at one of input terminals, the output L(n/2) of the (n/2)th-stage latch circuit through a first inverter and inputting, at the other input terminal, an output of the second OR logic gate; a first P-channel transistor having, as a drain, an input line L0 of the latch circuit group and a source set at a VCC level; a first N-channel transistor having, as a drain, the input line L0 of the latch circuit group and a source set at a GND level; a third NAND logic gate inputting an output of the first NAND logic gate and an output of the second NAND logic gate; a second P-channel transistor having, as a drain, a VCC-side power supply wiring VS supplying power to the sense amplifier and a source set at the VCC level; and a, second N-channel transistor having, as a drain, a GND-side power supply wiring GS of the sense amplifier and a source set at the GND level, and such that an output of the third logic gate is connected to a gate of the second P-channel transistor, the output of the third logic gate is connected to a gate of the second N-channel transistor through a second inverter, an output of the first logic gate is connected to a gate of the first P-channel transistor, and the output of the third logic gate is connected to a gate of the first N-channel transistor through a third inverter.
Moreover, the latch circuit can be constituted to comprise: a first transfer transistor inputting an output of the sense amplifier at a drain; a fourth inverter connected to a source of the first transfer transistor; circuit for inputting a latch pulse xc3x8n into a gate of an N-channel transistor of the first transfer transistor and inputting an inverted pulse of the latch pulse xc3x8n inverted by a fifth inverter, into a gate of a P-channel transistor; a second transfer transistor; circuit for inputting a latch pulse xc3x8 into a gate of a P-channel transistor of the second transfer transistor and inputting an inverted pulse of the latch pulse xc3x8 inverted by the fifth inverter, into a gate of an N-channel transistor; and circuit for inputting an output of the fourth inverter into a drain of the second transfer transistor through a sixth inverter, and for connecting the source of the first transfer transistor to a source of the second transfer transistor, and such that the output of the fourth inverter is an output of the latch circuit.
As stated above, according to the present invention, the power consumption of the sense amplifier is extremely reduced. In a conventional case of reading a four-level cell, for example, three word voltages of a first-stage voltage, a second-stage voltage and a third-stage voltage are inputted into the cell and the cell is read by a total of three sense amplifier operations. According to the present invention, by contrast, the four-level cell can be read by two sense amplifier operations. Hence, in case of the four-level cell, the power consumption of the sense amplifier is reduced to {fraction (2/3+L )}.